Electronic flasher circuits

ABSTRACT

Timing circuits comprising two complementary transistors regeneratively interconnected with an RC network.

Umtefl States Patent 1191 1111 3,803,515 Carlson Apr. 9, 1974 [5 ELECTRONIC FLASHER CIRCUITS 3,268,738 8/1966 Deavenport 307/273 2,986,709 5 1961 M 331 111 X [75] Inventor: Paul A. Carlson, New Provldence, 3,018,473 J1962 ggg 2 H 3,178,609 4/1965 Skirvin 331/111 x 3,348,167 10/1967 Gauld 331/111 [73] Ass'gnee' g g g Cuporamn 3,373,315 3/1968 Colman 307/288 x ewar 3,376,429 4/1968 Atkins et a1. 307/288 x [22] Filed: May 1972 3,139,556 6/1964 Grontkowski 331/108 A [2]] App]. Nu2 255,155 FOREIGN PATENTS OR APPLICATIONS 816,451 7/1959 Great Britain 315/200 A 603,522 4 1960 I 1 315 200 A 52 us. 01 331/111, 307/288, 307/293, my

51 I t Cl Primary Examiner-Stanley D. Miller, Jr. 1581 F110 05 500 00 51 33 171 10 113 R 108 A' Agent FiMTEYre Lucas 307/288, 293; 340/331, 340; 315/200 A [57] ABSTRACT 5 R fe n Cited Timing circuits comprising two compl0mentary tran- UNITED STATES PATENTS sistors regeneratively Interconnected wlth an RC net- 2,9l6,670 12/1959 Pederson 315/209 work 3.054.970 9/1962 Lace 331/1 11 12 Claims, 6 Drawing Figures ELECTRONIC FLASHER CIRCUITS BACKGROUND OF THE INVENTION The present invention relates to electronic timing circuits of simple construction and capable of controlling various load impedances such as lamps, buzzers, bells, relays and the like. Prior art devices include thermoresponsive bimetal switches and snap-action switches with an expansible pull wire. All of these devices controlled the opening and closing of at least one pair of contacts in the load current path. Such contacts are subject to wear and deterioration from corrosion, abrasion and electrical arcing, and thereby place inherent limitations on the useful life of the device of which they are a part. Also, when such devices are utilized as intermittent circuit breakers (flashers), the adjustability of rate and ratio is confined to relatively narrow ranges by inherent mechanical limitations. In addition, prior-art thermoresponsive switches of mechanical nature are apt to go out of adjustment upon mechanical impact impact or due to variations in ambient temperature or changes in vane (buckling member) characteristics.

SUMMARY OF THE INVENTION The present invention is embodied in and carried out by electronic timing circuits in which two complementary transistors are regeneratively interconnected with an RC network to enable either periodic or selective energization and de-energization of one or more load impedances. These circuits are capable of adjustment over wide ranges, are virtually shockproof, and exhibit a high degree of insensitivity to changes in ambient temperature. Due to the elimination of contacts, the useful life of these circuits is far greater than prior-art devices employing contacts.

BRIEF DESCRIPTION OF THE DRAWING The present invention will be better understood when the written description thereof is read in connection with the accompanying drawing, of which:

FIG. 1 is a schematic wiring diagram of a first embodiment of the invention, showing the connections of its terminals to a source of power and a load;

FIG. 2 comprises a series of graphs representative of the voltages at various points in the circuit of FIG. 1 through a full cycle, said graphs being on a common time base;

FIG. 3 is a schematic wiring diagram of a second embodiment of the invention, showing the connections of its terminals to a source of power and two loads;

FIG. 4 is a schematic wiring diagram of a third embodiment of the invention, showing the connections of its terminals to a source of power and two loads;

FIG. 5 is a schematic wiring diagram of a fourth embodiment of the invention, showing the connections of its various terminals to a source of power and a load; and

FIG. 6 is a schematic wiring diagram of a fifth embodiment of the invention, showing the connections of its various terminals to a source of power and two loads.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring now specifically to the first embodiment shown in FIG. 1 and the related graphs shown in FIG. 2, when switch S is closed, the source of electromotive force (EMF) consisting of battery B is connected to terminal T1 of the timing circuit. Thus, a small current begins to flow across the emitter-base junction of the normally non-conductive transistor Q1, and through resistances R1, R2 and R3 across the base-emitter junction of normally non-conductive transistor O2 to ground. The collector-emitter junction of O2 is made more conductive by this small turn-on current, thus enhancing turn-on current flow to Q1 across its emitterbase junction through R1 and the collector-emitter junction of Q2. Consequently, the emitter-collector junction O1 is made more conductive, and current flows across that junction through Cl, which acts as a very low impedance since it is initially uncharged, and through R3 and the base-emitter junction of Q2. This relatively large turn-on current causes O2 to become fully conductive, thereby enabling maximum flow of turn-on current across the emitter-base junction of O1 through R1 and the collector-emitter junction of O2 to ground. Thus, O1 is also rendered fully conductive, causing the collector voltage of O1 to rise to a value a fraction of a volt less than the output voltage of battery B and thereby energizing load Ll. Both Q1 and Q2 are rendered conductive virtually instantaneously with the closing of switch S due to the regenerative effect of the currents flowing through each transistor on the other. As shown in FIG. 2A, the voltage at the collector of Q1 rises sharply to a voltage nearly equal to that of battery 8 when switch S is closed at time T The voltage at the junction of Cl-R2-R3 shown in FIG. 2B rises to substantially source voltage or higher at time T as a result of the collector of 01 being a fraction of a volt below source voltage (C1 being effectively a short circuit when uncharged), to which is added the IR drop across resistance R3 and the base-emitter junction of Q2. With Q1 and Q2 now being conductive, C1 is charged by current flowing across the emitter-collector junction of Q1 and through R2 and the collector-emitter junction of Q2, paralleled by R3 in series with the baseemitter junction of Q2, to ground. As Cl becomes charged between times T and T it has an increasingly greater limiting effect on the base and collector current in Q2. When the current flowing across the collectoremitter junction of Q2 drops below the minimum required emitter-base current of Q1, the loading effect of L1 begins to cause the Q1 collector voltage to drop off a fraction of a volt from its initial maximum value as shown in FIG. 2B just prior to time T As the voltage at the junction of Cl and L1 decreases in this manner, the positive voltage at the C1-R2-R3 junction also decreases. When Cl has charged to a level at which the voltage at the Cl-R2-R3 junction is too low to maintain Q2 conductive, the two transistors Q1 and Q2 are regeneratively cut ofi at time T As a result, the positive plate of CI is suddenly switched to ground potential from a positive voltage nearly equal to that of the source. Thus, the voltage at the Cl-R2-R3 junction becomes negative with respect to ground at time T as shown in FIG. 28, since it is the negative plate of C] which is connected to this junction and the positive plate is now grounded through the de-energized load L1. The negative voltage now appearing at the Cl-R2- R3 junction is applied to the base of Q2 through R3, thereby holding Q2 non-conductive. At time T capacitance Cl begins to discharge through the loop formed by the collector-base junction of Q1 and resistances R1 and R2. This discharge continues to time T at which time C1 is completely discharged and the C1-R2-R3 junction is at zero potential. Transistor Q2 is no longer held off by a negative base voltage, and a new cycle is initiated at time T The circuit continues to repeat the cycle just described until switch S is opened.

It should be noted that the base transport factor beta (B) of each of the transistors Q1 and Q2 is a significant parameter in the performance of this circuit. The higher the beta factor, the better able a transistor is to handle the load current demand imposed by L1 and the longer it will remain conductive. Where only a single load is controlled, the beta factor of the transistor to the collector of which the load is connected is of greater importance. Thus, the ON and OFF times of the circuit, i.e., the times when the load is energized and de-energized, respectively, are partially dependent upon the beta factors of transistors O1 and Q2 and upon the magnitude of the load current. ON time is controlled principally by the values of C1 and R3. The OFF time is controlled principally by the values of C1 and R1 plus R2. It should be noted that R1 could be positioned between terminal T1 and the emitter of transistor Q1, since its function is chiefly to limit current across the emitter-base junction of O1 and through the collector-emitter junction of Q2. With this modification, OFF time would be controlled by C1 and R2. It is also possible to combine the resistances represented by R1 and R3 in a single emitter-follower resistance of Q2.

Referring now specifically to the embodiment shown in FIG. 3, the circuit shown there is a modified version of the embodiment shown in FIG. 1. The first capacitance C1 has been removed, and a second capacitance C2 has been inserted between the junction of R1 and R2 and the collector of Q2. Also, a second load L2 has been connected between the emitter of Q1 and the collector of 02 through terminals T1 and T4. Both loads L1 and L2 are energized and de-energized in synchronization with one another, since 01 and Q2 are saturated and cut off during the same time periods. This circuit operates in much the same manner as the first embodiment shown in FIG. 1, with a few differences. The voltage waveform at the collector of O2 in the second embodiment is like that at the collector of O1 in the first embodiment (see FIG. 2A). Also, the capacitance C2 in the second embodiment is charged through the emitter-base junction of Q1 and R1, and through the emitter-collector junction of Q1 and R2. Capacitance C2 is discharged through the loop formed by R2, R3 and the base-collector junction of Q2. This circuit is subject to the same modification as the first embodiment.

Referring now specifically to the embodiment shown in FIG. 4, the circuit shown there is also a modified version of the embodiments shown in FIGS. 1 and 3. Two capacitances C l and C2 are employed in the same position in the circuit which those capacitances had in FIGS. 1 and 3, respectively. This modification has been found to afford better control of the duty cycle and output pulse width. As in the second embodiment shown in FIG. 3, this circuit can control two loads L1 and L2 which are energized and de-energized in synchronization. As in the second embodiment shown in FIG. 3, either load may be eliminated. In operation, the capacitance Cl is charged and discharged in the same manner as in the first embodiment shown in FIG. 1, and capacitance C2 is charged and discharged in the same manner as in the second embodiment shown in FIG. 3.

Referring now specifically to the embodiment shown in FIG. 5, this is a modification of the basic circuit shown in FIG. 1. This modified circuit is normally oscillatory when connected to a source of power (B+), but can be turned off by connection of a predetermined impedance. As shown, resistance R2 is broken up into two components, the first component R2a being permanently connected from the emitter of transistor Q1 through resistance R3 to the base of transistor Q2. The

second component R2b is selectively connectable to a control terminal TC connected to the junction of R2a, R3 and C1. The turn-off component R2b may be formed by a person touching the control terminal TC.

In operation, the circuit is normally oscillatory without keying resistance R2b connected between the control terminal TC and ground. This circuit differs in operation from the preceding embodiments in that the initial turn-on current for O2 is drawn from the source of power (B+) through the high resistance R2a and R3 across the base-emitter junction of O2 to ground. With Q2 being thus rendered more conductive, turn-on current flows across the emitter'base junction of Q1 through R1 and across the collector-emitter junction of O2 to ground. Thus, current can now flow across the emitter-collector junction of transistor Q1 and through capacitance C1, which acts as a virtual short circuit in its uncharged conduction, and through R3 across the base-emitter junction of O2 to ground, thus augmenting the turn-on current of Q2. In this fashion, the two transistors Q1 and Q2 are regeneratively turned on almost instantaneously with the source of power 8+ to terminal T1. As C1 accumulates an increasing amount of charge, it has a limiting effect .on the emittercollector current of Q1 and on the base-emitter current of Q2. As with the previous embodiments, transistors Q1 and 02 are regeneratively turned off when Cl has become sufficiently charged. Discharge of C1 then takes place through R1 and R2 and the base-collector junctions of Q1 and Q2, and the cycle is continously repeated.

Connection of resistance R2b from the control terminal TC to ground has the effect of diverting the initial turn-on current from the base of Q2, and therefore inhibits the oscillation of the circuit. The circuit could be modified so that it is normally non-oscillatory by removing R2a and making it selectively connectable between the source of power and the junction of Cl and R3, omitting R2b completely.

Referring now specifically to the embodiment shown in FIG. 6, this represents another modification of the basic circuits shown in FIGS. 1, 2 and 3. This modified circuit operates as a monostable multivibrator. By the application of either a positive-going pulse to control terminal TCl, or by application of a negative-going pulse to control terminal TC2, the loads L1 and L2 may be synchronously energized for a predetermined period of time. In the first instance, a positive pulse passing through coupling capacitance C2 and resistance R3 across the base-emitter junction of transistor Q2 will render that transistor momentarily conductive. Thus, turn-on current for transistor Q1 may flow across the emitter-base junction of Q1 and through resistance R1 and capacitance C1, which has its lower plate effectively connected to the source of power B+ through load L2 when Q2 is non-conductive. Consequently, Q1 becomes increasingly conductive and current flows across its emitter-collector junction and through R3 and the base-emitter junction of Q2 to ground, thus enhancing the conductivity of Q2. This increased conductivity results in increased current flow across the emitter-base junction of Q1 and through R1 and Cl across the collector-emitter junction of Q2. In this fashion, transistors Q1 and Q2 are regeneratively turned on virtually instantaneously upon the application of a control pulse at control terminal TC1. Optional resistance R1 acts to shunt current past capacitance C1 in order to lengthen the charging time of that capacitance, and thereby lengthen the on-time of transistors Q1 and Q2 and the period of energization of the loads L1 and L2. As capacitance C1 becomes increasingly charged with its lower plate connected to ground through the conductive transistor Q2, it will have an increasingly limiting effect on the current flowing across the emitterbase junction of Q1, thereby reducing the current flow across the emitter-collector junction of Q1 through R3 and across the base-emitter junction of Q2. When C1 is sufficiently charged, transistors Q1 and Q2 are regeneratively shut off, and the lower plate of capacitance Cl is again placed at source potential through load L2. Consequently, the upper plate of C1 goes to a voltage approximately double that of thesource of power B+. The optional diode D1 connected between the source of power and the upper plate of capacitance C 1 enables C1 to discharge virtually instantaneously through the power source. Thus, the recovery time of the circuit is minimized, so that it may readily handle closely-spaced input pulses.

The circuit will also operate in the foregoing manner it a negative input pulse is applied to control terminal TC2, thereby initiating current flow across the emitterbase junction of transistor Q1 and through R1 and C3 to the source of the pulse. This initial turn-on current for Q1 enables current flow across its emitter-collector junction through resistance R3 and across the baseemitter junction of Q2, thereby rendering that transistor more conductive. Consequently, current flow across the emitter-base junction of O1 is enhanced by flow through C1 and across the collector-emitter junction of Q2. In this fashion, transistors Q1 and Q2 are regeneratively turned on virtually instantaneously upon the application of the input pulse. Asbefore, the charg- I ing of C1 will eventually limit current flow and cause Q1 and Q2 to become regeneratively cut off. If the optional diode D1 were omitted, C1 could discharge across resistance R2. Alternatively, if optional resistance R2 were eliminated, C1 could discharge through diode D1.

There are numerous and varied uses for the several circuits disclosed herein. For example, the embodiments shown in FIGS. 1, 3 and 4 find ready application as flashers in automotive signal lamp circuits. In such applications, the battery B would correspond to the vehicle battery, the switch S would correspond to the turn signal switch or the emergency flasher switch, and the loads L1 and L2 would comprise light-emitting means such as incandescent lamps. The timing circuits enclosed by dotted lines in these figures can be constructed so compactly that they may be combined as a I unit with a signalling device such as an incandescent lamp, in which the timing circuit may be enclosed by the lamp base or socket. The embodiment shown in FIG. 5 is keyable by a resistance R2b which may be enclosed in an article of everyday wear, such as a ring, and the circuit could be employed to provide a pulsating input signal to control circuitry which would respond to said signal by opening a lock on an automobile car door, for example. The embodiment shown in FIG. 7 may be employed in any of the various applications for a monostable multivibrator, e.g., to standardize pulses of random widths.

The advantages of the present invention, as well as certain changes and modifications of the disclosed embodiments thereof, will be readily apparent to those skilled in the art. It is the applicants intention to cover all those changes and modifications which could be made to the embodiments of the invention herein chosen for the purposes of the disclosure without departing from the spirit and scope of the invention.

What is claimed is:

1. An electronic flasher circuit comprising:

1. a first transistor of a first conductivity type;

2. a second transistor of a second conductivity type;

and

3. network means regeneratively interconnecting said first and said second transistors so that all transistor turn-on currents are confined to paths through said first and second transistors, said network means being operative, when a source of power and at least one load are connected to said timing circuit, to cause said transistors to alternate synchronously between the conductive and the non-conductive states and thereby alternately energize and de-energize said at least one load.

2. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resistance connected betweenthe bases of said first and second transistors, a first terminal of said at least one resistance also being connected to the collector of said second transistor and the second terminal of said at least one resistance also being connected through a capacitance to the collector of said first transistor.

3. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected to the collector of said second transistor and the junction of said second and third resistances being connected through a capacitance to the collector of said first transistor.

4. An electronic flasher circuit according to claim 3 and further comprising a load connected between the collector of said first transistor and the emitter of said second transistor.

5. An electronic flasher circuit according to claim 1 and further comprising a load connected between the collector of said first transistor and the emitter of said second transistor.

6. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resistance connected between the bases of said first and second transistors, the first terminal of said at least one resistance also being connected through a capacitance to the collector of said second transistor and the second terminal of said at least one resistance also being connected to the collector of said first transistor.

7. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected through a capacitance to the collector of the said second transistor and the junction of said second and third resistances being connected to the collector of said first transistor.

8. An electronic flasher circuit according to claim 6 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor.

9. An electronic flasher circuit according to claim 1 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor.

10. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resitance connected between the bases of said first and second transistors, the first terminal of said at least one resistance also being connected through a second capacitance to the collector of said second transistor, and the second terminal of said at least one resistance also being connected through a first capacitance to the collector of said first transistor.

11. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected through a second capacitance to the collector of said second transistor and the junction of said second and third resistances being connected through a first capacitance to the collector of said first transistor.

12. An electronic flasher circuit according to claim 11 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor. 

1. An electronic flasher circuit comprising:
 1. a first transistor of a first conductivity type;
 2. a second transistor of a second conductivity type; and
 3. network means regeneratively interconnecting said first and said second transistors so that all transistor turn-on currents are confined to paths through said first and second transistors, said network means being operative, when a source of pOwer and at least one load are connected to said flasher circuit, to cause said transistors to alternate synchronously between the conductive and the non-conductive states and thereby alternately energize and de-energize said at least one load.
 2. a second transistor of a second conductivity type; and
 2. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resistance connected between the bases of said first and second transistors, a first terminal of said at least one resistance also being connected to the collector of said second transistor and the second terminal of said at least one resistance also being connected through a capacitance to the collector of said first transistor.
 3. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected to the collector of said second transistor and the junction of said second and third resistances being connected through a capacitance to the collector of said first transistor.
 3. network means regeneratively interconnecting said first and said second transistors so that all transistor turn-on currents are confined to paths through said first and second transistors, said network means being operative, when a source of pOwer and at least one load are connected to said flasher circuit, to cause said transistors to alternate synchronously between the conductive and the non-conductive states and thereby alternately energize and de-energize said at least one load.
 4. An electronic flasher circuit according to claim 3 and further comprising a load connected between the collector of said first transistor and the emitter of said second transistor.
 5. An electronic flasher circuit according to claim 1 and further comprising a load connected between the collector of said first transistor and the emitter of said second transistor.
 6. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resistance connected between the bases of said first and second transistors, the first terminal of said at least one resistance also being connected through a capacitance to the collector of said second transistor and the second terminal of said at least one resistance also being connected to the collector of said first transistor.
 7. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected through a capacitance to the collector of the said second transistor and the junction of said second and third resistances being connected to the collector of said first transistor.
 8. An electronic flasher circuit according to claim 6 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor.
 9. An electronic flasher circuit according to claim 1 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor.
 10. An electronic flasher circuit according to claim 1 wherein said network means comprises at least one resitance connected between the bases of said first and second transistors, the first terminal of said at least one resistance also being connected through a second capacitance to the collector of said second transistor, and the second terminal of said at least one resistance also being connected through a first capacitance to the collector of said first transistor.
 11. An electronic flasher circuit according to claim 1 wherein said network means comprises first, second and third resistances connected in series between the bases of said first and second transistors, the junction of said first and second resistances being connected through a second capacitance to the collector of said second transistor and the junction of said second and third resistances being connected through a first capacitance to the collector of said first transistor.
 12. An electronic flasher circuit according to claiM 11 and further comprising a first load connected between the collector of said first transistor and the emitter of said second transistor, and a second load connected between the collector of said second transistor and the emitter of said first transistor. 